BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:Australia/Melbourne
X-LIC-LOCATION:Australia/Melbourne
BEGIN:DAYLIGHT
TZOFFSETFROM:+1000
TZOFFSETTO:+1100
TZNAME:AEDT
DTSTART:19721003T020000
RRULE:FREQ=YEARLY;BYMONTH=4;BYDAY=1SU
END:DAYLIGHT
BEGIN:STANDARD
DTSTART:19721003T020000
TZOFFSETFROM:+1100
TZOFFSETTO:+1000
TZNAME:AEST
RRULE:FREQ=YEARLY;BYMONTH=10;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20240214T070243Z
LOCATION:Meeting Room C4.11\, Level 4 (Convention Centre)
DTSTART;TZID=Australia/Melbourne:20231212T171800
DTEND;TZID=Australia/Melbourne:20231212T173300
UID:siggraphasia_SIGGRAPH Asia 2023_sess122_papers_438@linklings.com
SUMMARY:Locally-Adaptive Level-of-Detail for Hardware-Accelerated Ray Trac
 ing
DESCRIPTION:Technical Communications, Technical Papers\n\nJacob Haydel (Un
 iversity of Utah); Cem Yuksel (University of Utah, Roblox); and Larry Seil
 er (Independent)\n\nWe introduce an adaptive level-of-detail technique for
  ray tracing triangle meshes that aims to reduce the memory bandwidth used
  during ray traversal, which can be the bottleneck for rendering time with
  large scenes and the primary consumer of energy. We propose a specific da
 ta structure for hierarchically representing triangle meshes, allowing loc
 alized decisions for the desired mesh resolution per ray. Starting with th
 e lowest-resolution triangle mesh level, higher-resolution levels are gene
 rated by tessellating each triangle into four via splitting its edges with
  arbitrarily-placed vertices. We fit the resulting mesh hierarchy into a s
 pecialized acceleration structure to perform on-the-fly tessellation level
  selection during ray traversal. Our structure reduces both storage cost a
 nd data movement during rendering, which are the main consumers of energy.
  It also allows continuous transitions between detail levels, while locall
 y adjusting the mesh resolution per ray and preserving watertightness. We 
 present how this structure can be used with both primary and secondary ray
 s for reflections and shadows, which can intersect with different tessella
 tion levels, providing consistent results. We also propose specific hardwa
 re units to cover the cost of additional compute needed for level-of-detai
 l operations. We evaluate our method using a cycle-accurate simulation of 
 a custom ray tracing hardware architecture. Our results show that, as comp
 ared to traditional bounding volume hierarchies, our method can provide mo
 re than an order of magnitude reduction in energy use and render time, giv
 en sufficient computational resources.\n\nRegistration Category: Full Acce
 ss\n\nSession Chair: Bin Chen (Max-Planck-Institut für Informatik, D4: Com
 puter Graphics)
URL:https://asia.siggraph.org/2023/full-program?id=papers_438&sess=sess122
END:VEVENT
END:VCALENDAR